Combinatorial optimization: algorithms and complexity
Combinatorial optimization: algorithms and complexity
Automatic sizing of power/ground (P/G) networks in VLSI
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Optimum design of reliable IC power networks having general graph topologies
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Power and ground network topology optimization for cell based VLSIs
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Integrated power supply planning and floorplanning
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Fast power/ground network optimization based on equivalent circuit modeling
Proceedings of the 38th annual Design Automation Conference
Congestion-driven codesign of power and signal networks
Proceedings of the 39th annual Design Automation Conference
Fast analysis and optimization of power/ground networks
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Area minimization of power distribution network using efficient nonlinear programming techniques
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Challenges in power-ground integrity
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
On-chip power supply network optimization using multigrid-based technique
Proceedings of the 40th annual Design Automation Conference
Distributed sleep transistor network for power reduction
Proceedings of the 40th annual Design Automation Conference
Analysis and Optimization of Power Grids
IEEE Design & Test
RC Power Bus Maximum Voltage Drop in Digital VLSI Circuits
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Power Bus Maximum Voltage Drop in Digital VLSI Circuits
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Thermal and Power Integrity Based Power/Ground Networks Optimization
Proceedings of the conference on Design, automation and test in Europe - Volume 2
On optimal physical synthesis of sleep transistors
Proceedings of the 2004 international symposium on Physical design
Optimal placement of power supply pads and pins
Proceedings of the 41st annual Design Automation Conference
Efficient power/ground network analysis for power integrity-driven design methodology
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 41st annual Design Automation Conference
Optimal planning for mesh-based power distribution
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Power/Ground Mesh Area Optimization Using Multigrid-Based Technique
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Distributed sleep transistor network for power reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scaling Analysis of On-Chip Power Grid Voltage Variations in Nanometer Scale ULSI
Analog Integrated Circuits and Signal Processing
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Current-driven wire planning for electromigration avoidance in analog circuits
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
VLSI on-chip power/ground network optimization considering decap leakage currents
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Analysis and optimization of power-gated ICs with multiple power gating configurations
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A novel technique for incremental analysis of on-chip power distribution networks
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Stochastic current prediction enabled frequency actuator for runtime resonance noise reduction
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Reliability analysis and optimization of power-gated ICs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Runtime resonance noise reduction with current prediction enabled frequency actuator
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |