Minimal area sizing of power and ground nets for VLSI circuits
Proceedings of the fourth MIT conference on Advanced research in VLSI
An automated design of minimum-area IC power/ground nets
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
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DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
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DAC '98 Proceedings of the 35th annual Design Automation Conference
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
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ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
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Proceedings of the 41st annual Design Automation Conference
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Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
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ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
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Proceedings of the 2008 Asia and South Pacific Design Automation Conference
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ACM Transactions on Design Automation of Electronic Systems (TODAES)
Locality-driven parallel power grid optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reliability-Driven Power/Ground Routing for Analog ICs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Proceedings of the International Conference on Computer-Aided Design
Eagle-eye: a near-optimal statistical framework for noise sensor placement
Proceedings of the International Conference on Computer-Aided Design
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This paper presents a fast and efficient method for sizing power/ground networks. No restrictions on network topology or number of supplying pads are imposed. Wire widths are calculated such that the weighted area of wire segments is minimized while electromigration and voltage drops constraints are fulfilled. The algorithm proposed here runs 50% faster than the best methods reported for tree type network topologies.