Minimal area sizing of power and ground nets for VLSI circuits
Proceedings of the fourth MIT conference on Advanced research in VLSI
The construction of minimal area power and ground nets for VLSI circuits
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Automatic placement a review of current techniques (tutorial session)
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Introduction to VLSI Systems
Laying the power and ground wires on a VLSI chip
DAC '83 Proceedings of the 20th Design Automation Conference
Computation of power supply nets in VLSI layout
DAC '81 Proceedings of the 18th Design Automation Conference
Automatic sizing of power/ground (P/G) networks in VLSI
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Multi-pads, single layer power net routing in VLSI circuits
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Analyzing CMOS power supply networks using Ariel
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A current driven routing and verification methodology for analog applications
Proceedings of the 37th Annual Design Automation Conference
Single step current driven routing of multiterminal signal nets for analog applications
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Electromigration Avoidance in Analog Circuits: Two Methodologies for Current-Driven Routing
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
A dynamic programming approach to the power supply net sizing problem
EURO-DAC '90 Proceedings of the conference on European design automation
Current-driven wire planning for electromigration avoidance in analog circuits
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
| Hi-index | 0.00 |
Given tree topologies for routing power/ground (p/g) nets in integrated circuits, this paper formulates and solves the problem of determining the widths of the branches of the trees. Constraints are developed in order to maintain proper logic levels and switching speed, to prevent electromigration, and to satisfy certain design rule and regularity requirements. The area required by the p/g distribution system is minimized subject to these constraints. Some case studies are also presented.