A current driven routing and verification methodology for analog applications

Authors:
Thorsten Adler;Hiltrud Brocke;Lars Hedrich;Erich Barke
Affiliations:
Infineon Technologies AG, St.-Martin-Str. 76, D-81541 Munich, Germany;Institute of Microelectronic Systems, University of Hanover, Appelstr. 4, D-30167 Hanover, Germany;Institute of Microelectronic Systems, University of Hanover, Appelstr. 4, D-30167 Hanover, Germany;Institute of Microelectronic Systems, University of Hanover, Appelstr. 4, D-30167 Hanover, Germany
Venue:
Proceedings of the 37th Annual Design Automation Conference
Year:
2000

Citing 7
Cited 7

An automated design of minimum-area IC power/ground nets

DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Combinatorial algorithms for integrated circuit layout

Combinatorial algorithms for integrated circuit layout
Numerical recipes in C (2nd ed.): the art of scientific computing

Numerical recipes in C (2nd ed.): the art of scientific computing
Single step current driven routing of multiterminal signal nets for analog applications

DATE '00 Proceedings of the conference on Design, automation and test in Europe
Computation of power supply nets in VLSI layout

DAC '81 Proceedings of the 18th Design Automation Conference
A solution to line-routing problems on the continuous plane

DAC '69 Proceedings of the 6th annual Design Automation Conference
Finding obstacle-avoiding shortest paths using implicit connection graphs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Reliability-driven layout decompaction for electromigration failure avoidance in complex mixed-signal IC designs

Proceedings of the 41st annual Design Automation Conference
Current-driven wire planning for electromigration avoidance in analog circuits

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Optimal wiring topology for electromigration avoidance considering multiple layers and obstacles

Proceedings of the 19th international symposium on Physical design
SIAR: splitting-graph-based interactive analog router

Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Electromigration-aware routing for 3D ICs with stress-aware EM modeling

Proceedings of the International Conference on Computer-Aided Design
Simultaneous analog placement and routing with current flow and current density considerations

Proceedings of the 50th Annual Design Automation Conference
WiT: optimal wiring topology for electromigration avoidance

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

We present a new methodology for current driven routing and layout verification for analog applications used to avoid defects due to electromigration.The methodology presented uses a commercial simulator to calculate the current flow at all terminals of the analog circuit. Afterwards maximum currents per terminal are extracted and used as guidance for the Current Driven Router (CDR) which is capable of routing analog multiterminal signal nets with current driven wire widths.The Current Density Simulator (CDS) is used to compute and verify current densities in layouts that were generated using a 'standard' routing methodology.