Voronoi diagram for multiply-connected polygonal domains 11: implementation and application
IBM Journal of Research and Development
Resistance extraction using a routing algorithm
DAC '93 Proceedings of the 30th international Design Automation Conference
A practical approach to static signal electromigration analysis
DAC '98 Proceedings of the 35th annual Design Automation Conference
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A current driven routing and verification methodology for analog applications
Proceedings of the 37th Annual Design Automation Conference
Current-driven wire planning for electromigration avoidance in analog circuits
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interconnect and current density stress: an introduction to electromigration-aware design
Proceedings of the 2005 international workshop on System level interconnect prediction
introduction to electromigration-aware physical design
Proceedings of the 2006 international symposium on Physical design
Electromigration and its impact on physical design in future technologies
Proceedings of the 2013 ACM international symposium on International symposium on physical design
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The negative effect of electromigration on signal and power line lifetime and functional reliability is an increasingly important problem for the physical design of integrated circuits. We present a new approach that addresses this electromigration issue by considering current density and inhomogeneous current-flow within arbitrarily shaped metallization patterns during physical design. Our proposed methodology is based on a post-route modification of critical layout structures that utilizes current-density data from a previously performed current-density verification. It is especially tailored to overcome the lack of current-flow consideration within existing routing tools. We also present experimental results obtained after successfully integrating our methodology into a commercial IC design flow.