An automated design of minimum-area IC power/ground nets
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Power and ground network topology optimization for cell based VLSIs
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A floorplan-based planning methodology for power and clock distribution in ASICs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A current driven routing and verification methodology for analog applications
Proceedings of the 37th Annual Design Automation Conference
Single step current driven routing of multiterminal signal nets for analog applications
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Laying the power and ground wires on a VLSI chip
DAC '83 Proceedings of the 20th Design Automation Conference
Electromigration Avoidance in Analog Circuits: Two Methodologies for Current-Driven Routing
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 41st annual Design Automation Conference
Interconnect and current density stress: an introduction to electromigration-aware design
Proceedings of the 2005 international workshop on System level interconnect prediction
introduction to electromigration-aware physical design
Proceedings of the 2006 international symposium on Physical design
Optimal wiring topology for electromigration avoidance considering multiple layers and obstacles
Proceedings of the 19th international symposium on Physical design
Reliability-Driven Power/Ground Routing for Analog ICs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Simultaneous analog placement and routing with current flow and current density considerations
Proceedings of the 50th Annual Design Automation Conference
WiT: optimal wiring topology for electromigration avoidance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Electromigration due to insufficient wire width can cause the premature failure of a circuit. The ongoing reduction of circuit feature sizes has aggravated the problem over the last couple of years, especially with analog circuits. It is therefore an important reliability issue to consider current densities already in the physical design stage. We present a new methodology capable of routing analog multi-terminal signal nets with current-dependent wire widths. It is based on current-driven wire planning which effectively determines all branch currents prior to detailed routing. We also discuss successful applications of our methodology in commercial analog circuit design.