WiT: optimal wiring topology for electromigration avoidance

  • Authors:
  • Iris Hui-Ru Jiang;Hua-Yu Chang;Chih-Long Chang

  • Affiliations:
  • Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan;Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan and VIA Technologies, Inc., New Taipei, Taiwan;Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan

  • Venue:
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Year:
  • 2012

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Abstract

Due to excessive current densities, electromigration (EM) may trigger a permanent open- or short-circuit failure in signal wires or power networks in analog or mixed-signal circuits. As the feature size keeps shrinking, this effect becomes a key reliability concern. Hence, in this paper, we focus on wiring topology generation for avoiding EM at the routing stage. Prior works tended towards heuristics; on the contrary, we first claim this problem belongs to class P instead of class NP-hard. Our breakthrough is, via the proof of the greedy-choice property, we successfully model this problem on a multi-source multi-sink flow network and then solve it by a strongly polynomial time algorithm. Experimental results prove the effectiveness and efficiency of our algorithm.