Electromigration and stress-induced voiding in fine Al and Al-alloy thin-filmed lines
IBM Journal of Research and Development
A Standard Cell Library for Student Projects
MSE '03 Proceedings of the 2003 International Conference on Microelectronics Systems Education
Circuit Level Reliability Analysis of Cu Interconnects
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
A Layout Sensitivity Model for Estimating Electromigration-vulnerable Narrow Interconnects
Journal of Electronic Testing: Theory and Applications
WiT: optimal wiring topology for electromigration avoidance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Under similar test conditions, the electromigration reliability of Al and Cu metallization interconnect trees demonstrates significant differences because of the differences in interconnect architectural schemes. In Cu technology, the low critical stress for void nucleation at the Cu and inter-level diffusion barrier, such as Si驴N驴, interface, leads to asymmetric failure characteristics based on via position in a line. Unlike Al technology, a (jL) product filtering algorithm with a classification of separate via-above and via-below treatments is required for Cu interconnect trees. Using the best estimates of material parameters and an analytical model, we have compared electromigration lifetimes of Al and Cu dual-damascene interconnect lines. A reliability CAD tool, SysRel, has been used to simulate full-chip reliability of the same circuit layout with different interconnect technologies. In typical circuit operating condition, Al bamboo lines have the best lifetime followed by Cu via-below, Cu via-above, and Al polygranular type lines.