Electromigration Reliability Comparison of Cu and Al Interconnects
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Thermal aware cell-based full-chip electromigration reliability analysis
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Proceedings of the 43rd annual Design Automation Conference
Elmore model for energy estimation in RC trees
Proceedings of the 43rd annual Design Automation Conference
Interconnect lifetime prediction for reliability-aware systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Layout Sensitivity Model for Estimating Electromigration-vulnerable Narrow Interconnects
Journal of Electronic Testing: Theory and Applications
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
An approach for lifetime reliability analysis using theorem proving
Journal of Computer and System Sciences
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Copper (Cu) based interconnect technology is expected to meet some of the challenges of technology scaling in the pursuit of higher performance. However, Cu interconnects are still susceptible to electromigration-induced failure over time. We describe a new hierarchicalapproach for predicting the reliability of Cu-based interconnects in circuit layouts, and present an RCAD tool, SysRel, for such an analysis. We propose a (jL) product filtering algorithm with a classification of separate via-above and via-below treatments in Cu interconnect trees. After the filtering of immortal trees, a default model is applied to the remaining trees to compute reliability figures for individual units. SysRel utilizes joint stochastic reliability metrics based on the desired lifetime of a chip and combines reliability figures from individual fundamental reliability units. Simulation results with a 32-bit comparator circuit layout demonstrate the significance of our methodology in selectively identifying critical nets and their impacts on overall reliability.