Thermal aware cell-based full-chip electromigration reliability analysis

Authors:
Syed M. Alam;Donald E. Troxel;Carl V. Thompson
Affiliations:
Freescale Semiconductor Inc., Austin, TX;Massachusetts Institute of Technology, Cambridge, MA;Massachusetts Institute of Technology, Cambridge, MA
Venue:
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Year:
2005

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Abstract

A hierarchical scheme with cells and modules is crucial for managing design complexity during a large integrated circuit design. We present a methodology for thermal aware cell-based electromigration analysis suitable for integrating electromigration reliability analysis into a conventional IC design flow. A block or cell is characterized for reliability while it is characterized for power and timing. Reusing cell characterization data significantly reduces computational load while analyzing a full-chip layout. During full-chip analysis, we compute a layout-level temperature profile from cell power dissipations using a Fast Fourier Transform based algorithm. The described full-chip reliability assessment methodology has been implemented in an interconnect reliability CAD tool. We have exercised the tool to demonstrate performance-reliability tradeoff and the significance of thermal-aware reliability analysis for true reliability aware design.