Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Thermal aware cell-based full-chip electromigration reliability analysis
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
iTEM: a temperature-dependent electromigration reliability diagnosis tool
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Towards a chip level reliability simulator for copper/low-k backend processes
Proceedings of the Conference on Design, Automation and Test in Europe
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We have developed a set of methodologies for thermal aware circuit-level reliability analysis with either Al or Cu metallization in a circuit layout and implemented it in a public domain reliability CAD tool, SysRel. SysRel utilizes a hierarchical reliability analysis flow, with interconnect trees treated as the fundamental reliability unit, that sufficiently captures the differences in electromigration failure between Al and Cu metallizations. Under similar test conditions, the electromigration reliability of Al and Cu interconnect trees demonstrates significant differences because of the differences in interconnect architectural schemes. Using the best estimates of material parameters and an analytical model, we present a detail comparison of electromigration reliability of a sample test-structure as well as of actual circuit layouts with Al and Cu dual-damascene interconnect systems. We also demonstrate fast thermal-analysis in SysRel for circuit performance driven chip-level reliability assessment.