Modified booth truncated multipliers
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Electromigration Reliability Comparison of Cu and Al Interconnects
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Thermal aware cell-based full-chip electromigration reliability analysis
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Constant addition with flagged binary adder architectures
Integration, the VLSI Journal
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A standard-cell library for MOSIS scaleable CMOS ruleshas been developed. It is intended for use with SynopsysDesign Compiler, Cadence Silicon Ensemble, and CadenceVirtuoso or Magic. The library is targeted for the AMI0.5µm process, which currently offers the smallest featuresize in the MOSIS educational program. The library also includesI/O pad cells and fully places and routes a padframeif desired. All steps in the design flow are fully automatedwith only three scripts and have been tested successfully ina large VLSI design class at the Illinois Institute of Technology.To customize and run these three scripts, for a givendesign, typically takes less than five minutes, since all detailsare transparent to the students, allowing them to focuson the design instead of worrying about the tools.