On the Time Required to Perform Addition
Journal of the ACM (JACM)
Journal of the ACM (JACM)
The Flagged Prefix Adder and its Applications in Integer Arithmetic
Journal of VLSI Signal Processing Systems
A Reduced-Area Scheme for Carry-Select Adders
IEEE Transactions on Computers
Techniques for Fast CMOS-based Conditional Sum Adders
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
A Standard Cell Library for Student Projects
MSE '03 Proceedings of the 2003 International Conference on Microelectronics Systems Education
A Regular Layout for Parallel Adders
IEEE Transactions on Computers
Impact of supply voltage variations on full adder delay: analysis and comparison
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations
IEEE Transactions on Computers
Analysis and comparison on full adder block in submicron technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A new construction adder based on Chinese abacus algorithm
Computers and Electrical Engineering
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The goal of this paper is to present architectures that provide the flexibility within a regular adder to augment/decrement the sum of two numbers by a constant. This flexibility adds to the functionality of a regular adder, achieving a comparable performance to conventional designs, thereby eliminating the need of having a dedicated adder unit to perform similar tasks. This paper presents an adder design to accomplish three-input addition if the third operand is a constant. This is accomplished by the introduction of flag bits. Such designs are called Enhanced Flagged Binary Adders (EFBA). It also examines the effect on the performance of the adder when the operand size is expanded from 16 bits to 32 and 64 bits. A detailed analysis has been provided to compare the performance of the new designs with carry-save adders in terms of delay, area and power.