Yield modeling and BEOL fundamentals
Proceedings of the 2001 international workshop on System-level interconnect prediction
Pre-layout prediction of interconnect manufacturability
Proceedings of the 2001 international workshop on System-level interconnect prediction
Mechanism of electromigration failure in submicron Cu interconnects
Journal of Electronic Materials - Materials and processes for submicron technologies II
Calibration of Open Interconnect Yield Models
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Circuit Level Reliability Analysis of Cu Interconnects
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
CMOS Electronics: How It Works, How It Fails
CMOS Electronics: How It Works, How It Fails
Logic Synthesis for Manufacturability
IEEE Design & Test
The Impact of Technology Scaling on Lifetime Reliability
DSN '04 Proceedings of the 2004 International Conference on Dependable Systems and Networks
Electromigration Reliability Comparison of Cu and Al Interconnects
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
IBM Journal of Research and Development - POWER5 and packaging
Stochastic interconnect layout sensitivity model
Proceedings of the 2007 international workshop on System level interconnect prediction
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During back-end manufacturing process of IC, intervention of spot defects induces extra and missing material of interconnects causing circuit failures. Interconnect narrowing occurs when spot defects induce interconnects missing material without resulting in a complete cut. The narrow sites of defective interconnects favor electromigration that makes narrow interconnects more likely to induce a chip failure than regular interconnects. In this paper, an innovative layout sensitivity model accounting for "narrow" defects is derived. The paper also pioneers estimation of the probability of narrow interconnects in the die. The layout sensitivity model for narrow interconnects is tested and compared to actual and simulated data. Our layout sensitivity model predicts the probability of narrowing with 3.1% error, on average. The model is then combined with electromigration constraints to predict mean-time-to-failure of chips manufactured in future technologies down to 32 nm node. The paper concludes with some other possible applications of the narrow interconnect predictive model.