Stochastic interconnect layout sensitivity model

Authors:
Payman Zarkesh-Ha;Ken Doniger
Affiliations:
University of New Mexico, Albuquerque, NM;Abbott Diabetes Care, Alameda, CA
Venue:
Proceedings of the 2007 international workshop on System level interconnect prediction
Year:
2007

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Abstract

Semiconductor manufacturing yield is determined by the defect density and critical area i.e. that portion of the layout in which the occurrence of a defect results in yield loss. In this paper, we define layout sensitivity as the ratio of critical area to the layout area. Utilizing the basic probability theory, a rigorous derivation of layout sensitivity for random logic network is performed. This model is compared to actual critical area distributions for a modern microprocessor design. A methodology to calculate the layout sensitivity pattern for a complex layout is proposed.