A net-oriented method for realistic fault analysis
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Critical area computation—a new approach
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Hidden surface removal using polygon area sorting
SIGGRAPH '77 Proceedings of the 4th annual conference on Computer graphics and interactive techniques
Fast Multi-Layer Critical Area Computation
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
A Comparison of Efficient Dot Throwing and Shape Shifting Extra Material Critical Area Estimation
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Impact of Simulation Parameters on Critical Area Analysis
DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
An introduction to OpenAccess: an open source data model and API for IC design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Stochastic interconnect layout sensitivity model
Proceedings of the 2007 international workshop on System level interconnect prediction
Yield prediction by sampling IC layout
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Due to inefficient calculation in current critical area analyzer, in this work we present a method of extracting critical area for short faults from the mask layout of an integrated circuit. The method is based on the concept of sampling framework and the geometry computation of critical area. By constructing the density table of layout, our weighted sampling approach can be more efficient, thus more suitable for the larger layout. The algorithm has been implemented on OpenAccess platform to allow efficient extraction of the critical area from an arbitrary mask layout. The results show that this method can reduce computation cost, and can still maintain the accuracy at the same time.