Voronoi diagrams—a survey of a fundamental geometric data structure
ACM Computing Surveys (CSUR)
Yield model for fault clusters within integrated circuits
IBM Journal of Research and Development
Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Linfinity Voronoi Diagrams and Applications to VLSI Layout and Manufacturing
ISAAC '98 Proceedings of the 9th International Symposium on Algorithms and Computation
A stochastic-based efficient critical area extractor on OpenAccess platform
Proceedings of the 19th ACM Great Lakes symposium on VLSI
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In this paper we present a new approach for computing the critical area for shorts in a circuit layout. The critical area calculation is the main computational problem in VLSI yield prediction. The method is based on the concept of Voronoi diagrams and computes the critical area for shorts (for all possible defect radii, assuming square defects) accurately in O(n log n) time, where n is the size of the input. The method is presented for rectilinear layouts but it is extendible to general layouts. As a byproduct we briefly sketch how to speed up the grid method of Wagner and Koren [16].