Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits

Authors:
W. Maly
Affiliations:
-
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2006

Citing 0
Cited 1

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ISPD '98 Proceedings of the 1998 international symposium on Physical design

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Abstract

In this paper, a modeling technique, describing IC manufacturing yield losses in terms of parameters characterizing lithography related point defects and line registration errors, is presented. Optimization of geometrical design rules, evaluation of VLSI IC artwork, and maximization of the wafer yield are discussed as examples illustrating applications and advantages of the proposed modeling technique.