Yield model for fault clusters within integrated circuits

Authors:
Charles H. Stapper
Affiliations:
IBM General Technology Division, Burlington facility, Essex Junction, Vermont
Venue:
IBM Journal of Research and Development
Year:
1984

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Abstract

Generalized negative binomial statistics turns out to be a model of the fault distribution in very large chips or wafers with internal defect clusters. This is expected to influence large chip and full wafer redundancy requirements. Furthermore, the yield appears to be affected by an experimental dependence of the average number of faults on chip area.