Large-area fault clusters and fault tolerance in VLSI circuits

Small-area fault clusters and fault tolerance in VLSI circuits

IBM Journal of Research and Development

Fault simulation programs for integrated-circuit yield estimations

IBM Journal of Research and Development

Synergistic Fault-Tolerance for Memory Chips

IEEE Transactions on Computers

Reliability, Reconfiguration, and Spare Allocation Issues in Binary-Tree Architectures Based on Multiple-Level Redundancy

IEEE Transactions on Computers

A New Class Of Efficient Algorithms For Reconfiguration Of Memory Arrays

IEEE Transactions on Computers

Yield modeling and BEOL fundamentals

Proceedings of the 2001 international workshop on System-level interconnect prediction

Yield Analysis of Reconfigurable Array Processors Based on Multiple-Level Redundancy

IEEE Transactions on Computers

Critical area extraction of extra material soft faults

DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

An Improved Analytical Yield Evaluation Method for Redundant RAM's

MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing

System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability

The effect on quality of non-uniform fault coverage and fault probability

ITC'94 Proceedings of the 1994 international conference on Test