DTR: a defect-tolerant routing algorithm
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Large-area fault clusters and fault tolerance in VLSI circuits
IBM Journal of Research and Development
Algorithms and Techniques for VLSI Layout and Synthesis
Algorithms and Techniques for VLSI Layout and Synthesis
Efficient Critical Area Algorithms and Their Application to Yield Improvement and Test Strategies
Proceedings of the The IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
An O (N log N) algorithm for Boolean mask operations
DAC '81 Proceedings of the 18th Design Automation Conference
Modeling of integrated circuit defect sensitivities
IBM Journal of Research and Development
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A method of extracting the extra material critical area of soft faults from an integrated circuit layout is presented. This has been implemented in the EYE tool allowing efficient extraction of the critical area from arbitrary mask layout. Results comparing defect sensitivity of a routing network modified to reduce defect sensitivity are reported. The application to defect related reliability is explored.