DAC '94 Proceedings of the 31st annual Design Automation Conference
Enhanced network flow algorithm for yield optimization
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Yield modeling and BEOL fundamentals
Proceedings of the 2001 international workshop on System-level interconnect prediction
Critical area extraction of extra material soft faults
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Incorporating Physical Design-For-Test Into Routing
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Should Yield be a Design Objective?
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
TROY: track router with yield-driven wire planning
Proceedings of the 44th annual Design Automation Conference
Concurrent wire spreading, widening, and filling
Proceedings of the 44th annual Design Automation Conference
Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Hi-index | 0.00 |
A new channel routing algorithm called DTR (Defect-Tolerant Routing) is investigated. This algorithm minimizes the total area and simultaneously maximizes the performance by reducing the critical area which can potentially be the source of logical faults caused by the bridging effects of spot defects. Experimental results show DTR produces less critical area than Yoshimura&Kuh's algorithm [1].