DTR: a defect-tolerant routing algorithm
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A Unified Negative-Binomial Distribution for Yield Analysis of Defect-Tolerant Circuits
IEEE Transactions on Computers
Enhanced network flow algorithm for yield optimization
DAC '96 Proceedings of the 33rd annual Design Automation Conference
On the effect of floorplanning on the yield of large area integrated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Incorporating Yield Enhancement into the Floorplanning Process
IEEE Transactions on Computers
Integrated Circuit Defect-Sensitivity: Theory and Computational Models
Integrated Circuit Defect-Sensitivity: Theory and Computational Models
VLSI Design for Manufacturing: Yield Enhancement
VLSI Design for Manufacturing: Yield Enhancement
Yield and Routing Objectives in Floorplanning
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Layer assignment for yield enhancement
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
IBM Journal of Research and Development
TROY: track router with yield-driven wire planning
Proceedings of the 44th annual Design Automation Conference
Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A yield-driven gridless router
Journal of Computer Science and Technology
On topology reconfiguration for defect-tolerant NoC-based homogeneous manycore systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Generation of yield-embedded Pareto-front for simultaneous optimization of yield and performances
Proceedings of the 47th Design Automation Conference
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The objectives of good chip design have traditionally included issues like performance, power and reliability. Yield is rarely considered during the design process, except in the design of memory ICs, where specific defect-tolerance techniques are incorporated into the architecture for yield enhancement.In order to make the case for establishing yield as another design objective we must first prove that a chip's yield can not only be affected, but consistently improved, by decisions made during the design process.