Fault Tolerance in VLSI Circuits
Computer
A general purpose multiple way partitioning algorithm
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
The Effect of Wire Length Minimization on Yield
Proceedings of the The IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Yield modeling and BEOL fundamentals
Proceedings of the 2001 international workshop on System-level interconnect prediction
Should Yield be a Design Objective?
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
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In this paper, two algorithms for layer assignment with the goal of yield enhancement are proposed. In the first, vias in an existing layout are moved in order to decrease its sensitivity to defects. A greedy algorithm for achieving this objective is presented. In the second, we formulate the layer assignment problem as a network bipartitioning problem. By applying the primal-dual algorithm (a variation of the Kernighan-Lin algorithm), the objective of critical area minimization can be achieved. These two methods are applied to a set of benchmark circuits to demonstrate their effectiveness.