IEEE Transactions on Computers
A reconfigurable and fault-tolerant VLSI multiprocessor array
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
The Hyeti Defect Tolerant Microprocessor: A Practical Experiment and its Cost-Effectiveness Analysis
IEEE Transactions on Computers
On the Yield of VLSI Processors with On-Chip CPU Cache
IEEE Transactions on Computers
IEEE Transactions on Computers
A new approach for critical area estimation in VLSI
Journal of Systems Architecture: the EUROMICRO Journal - Defect and fault tolerance in VLSI Systems
New Architecture and Algorithms for Degradable VLSI/WSI Arrays
COCOON '02 Proceedings of the 8th Annual International Conference on Computing and Combinatorics
Accurate yield estimation of circuits with redundancy
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Layer assignment for yield enhancement
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
ADTS: an array defect-tolerance scheme for wafer scale gate arrays
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
The effect of spot defects on the parametric yield of long interconnection lines
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
A Run-time Reconfiguration Algorithm for VLSI Arrays
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
14.1 Fast Self-Recovering Controllers
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
An improved reconfiguration algorithm for degradable VLSI/WSI arrays
Journal of Systems Architecture: the EUROMICRO Journal
Unified high-level synthesis and module placement for defect-tolerant microfluidic biochips
Proceedings of the 42nd annual Design Automation Conference
Reconfiguration Algorithms for Power Efficient VLSI Subarrays with Four-Port Switches
IEEE Transactions on Computers
A cache-defect-aware code placement algorithm for improving the performance of processors
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Integrated Row and Column Rerouting for Reconfiguration of VLSI Arrays with Four-Port Switches
IEEE Transactions on Computers
An Analysis for Fault-Tolerant 3D Processor Arrays Using 1.5-Track Switches
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
On topology reconfiguration for defect-tolerant NoC-based homogeneous manycore systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On the reconfiguration algorithm for fault-tolerant VLSI arrays
ICCS'03 Proceedings of the 2003 international conference on Computational science: PartIII
Proceedings of the Conference on Design, Automation and Test in Europe
Hybrid super/subthreshold design of a low power scalable-throughput FFT architecture
Transactions on High-Performance Embedded Architectures and Compilers IV
| Hi-index | 4.11 |
The defects that can occur when manufacturing VLSI ICs and the faults that can result are described. Some commonly used restructuring techniques for avoiding defective components are discussed. Several defect-tolerant designs of memory ICs, logic ICs, and wafer-scale circuits are presented. Yield models for predicting the yield of chips with redundancy are introduced, and the optimal amount of redundancy is determined.