IEEE Transactions on Computers
Fault-Tolerant Array Processors Using Single-Track Switches
IEEE Transactions on Computers
Fault Tolerance in VLSI Circuits
Computer
The Offset Cube: A Three-Dimensional Multicomputer Network Topology Using Through-Wafer Optics
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Computers
A Polynomial Time Algorithm for Reconfiguring Multiple-Track Models
IEEE Transactions on Computers
Proceedings of the The IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
A Routing Methodology for Achieving Fault Tolerance in Direct Networks
IEEE Transactions on Computers
Overview of the Blue Gene/L system architecture
IBM Journal of Research and Development
VLSI considerations for TESH: a new hierarchical interconnection network for 3-D integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An FPGA-based fault-tolerant 2D systolic array for matrix multiplications
Transactions on computational science XIII
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This paper deals with redundant 3D mesh processor arrays using 1.5-track switches, considering track and switch faults together with processor faults. Four variants are defined based on the distributions of spare PEs, and arrays of three variants have the same PE redundancies among them, but the fabrication-time costs are different. We investigate in detail how the reliability of a total system changes according to the reliabilities of tracks and switches as well as PEs, and show the concrete values of Mt and Ms, when the reliability of array are almost the same even if its variant is changed, and when it is not so, respectively, where Mt and Ms are the ratio of the hardware complexities of a PE and a track, and that of a PE and a contact point of a switch, respectively. Other results which are effective basis for the design of fault-tolerant 3D PE arrays using 1.5-TSs are given.