An FPGA-based fault-tolerant 2D systolic array for matrix multiplications

Authors:
Tadayoshi Horita;Itsuo Takanami
Affiliations:
Department of Information and Computer Science, Polytecnic University, Hashimotodai, Midori-ku, Japan and Ichinoseki national college of technology in former times, Iwate-ken, Japan;Department of Information and Computer Science, Polytecnic University, Hashimotodai, Midori-ku, Japan and Ichinoseki national college of technology in former times, Iwate-ken, Japan
Venue:
Transactions on computational science XIII
Year:
2011

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Abstract

This paper proposes a method to implement fault-tolerant self-reconfigurable 2D systolic arrays to calculate matrix multiplications on FPGAs. The array uses a 1.5-track switching network for reconfiguration. The array implemented is compared to the corresponding nonredundant case by simulations of concrete examples, in terms of hardware size, total array reliability where not only faults of processing elements but also faults in the 1.5-track switching network are considered, computation time and electricity consumption. The simulation results show that the fault-tolerant array is better than the corresponding nonredundant one, in terms of the total array reliability, even if faults in the 1.5-track switching network are not negligible. In Appendix, we discuss the relation between the fault rates of the proposed fault-tolerant array and the corresponding non-redundant one and show that the former can be significantly decreased for the array of large size.