Efficient reconfigurable techniques for VLSI arrays with 6-port switches
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An FPGA-based fault-tolerant 2D systolic array for matrix multiplications
Transactions on computational science XIII
Efficient techniques and hardware analysis for mesh-connected processors
ICA3PP'05 Proceedings of the 6th international conference on Algorithms and Architectures for Parallel Processing
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Massively parallel computers consisting of thousands of processing elements are expected to be high-performance computers in the next decade. One of the major issues in designing massively parallel computers is the reconfiguration strategy in order to provide an efficient fault tolerance mechanism to avoid defective processors in such large-scale systems. This paper develops a self-reconfigurable mechanism of mesh array for easy hardware implementation using local defect information. Compared to those of previous reconfigurable architecture, the proposed self-reconfigurable mechanism achieves almost the same system yields using only local defect information. A prototype of this self-reconfigurable array is implemented on FPGA and the hardware complexities are also discussed.