Scalable hardware implementing high-radix Montgomery multiplication algorithm
Journal of Systems Architecture: the EUROMICRO Journal
Safe-error attack on SPA-FA resistant exponentiations using a HW modular multiplier
ICISC'07 Proceedings of the 10th international conference on Information security and cryptology
High speed systolic Montgomery modular multipliers for RSA cryptosystems
IMCAS'06 Proceedings of the 5th WSEAS international conference on Instrumentation, measurement, circuits and systems
An FPGA-based fault-tolerant 2D systolic array for matrix multiplications
Transactions on computational science XIII
An optimised architecture for radix-2 Montgomery modular multiplication on FPGA
International Journal of High Performance Systems Architecture
Flexible design of a modular simultaneous exponentiation core for embedded platforms
ARC'13 Proceedings of the 9th international conference on Reconfigurable Computing: architectures, tools, and applications
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This paper describes a hardware architecture for modular multiplication operation which is efficient for bit-lengths suitable for both commonly used types of Public Key Cryptography (PKC) i.e. ECC and RSA Cryptosystems. The challenge of current PKC implementations is to deal with long numbers (160-2048 bits) in order to achieve system's efficiency, as well as security. RSA, still the most popular PKC, has at its root the modular exponentiation operation. Modular exponentiation consists of repeated modular multiplications, which is also the basic operation for ECC protocols. The solution proposed in this work uses a systolic array implementation and can be used for arbitrary precisions. We also present modular exponentiation based on Montgomery's Multiplication Method (MMM).