High speed systolic Montgomery modular multipliers for RSA cryptosystems

Authors:
Ravi Kumar Satzoda;Chip-Hong Chang;Ching-Chuen Jong
Affiliations:
Centre for High Performance Embedded Systems, Nanyang Technological University, Singapore;Centre for High Performance Embedded Systems, Nanyang Technological University, Singapore;Centre for High Performance Embedded Systems, Nanyang Technological University, Singapore
Venue:
IMCAS'06 Proceedings of the 5th WSEAS international conference on Instrumentation, measurement, circuits and systems
Year:
2006

Citing 4
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Abstract

Montgomery modular multiplication is one of the most important and frequently used techniques to accelerate the time consuming mathematical operations used in RSA cryptosystems. In this paper, a modified Montgomery modular multiplication algorithm is presented where the carry-save operations are split into two cycles so as to eliminate the generation of the data-dependent control signal from dominating the critical path. Two novel systolic Montgomery multipliers are designed based on the proposed algorithm. A bit-parallel pipelined architecture followed by a one dimensional variant are implemented on FPGA and evaluated against recently reported Montgomery multipliers implemented on the same platform. Improved results have been demonstrated in terms of area and throughput.