Accelerating the secure remote password protocol using reconfigurable hardware
Proceedings of the 1st conference on Computing frontiers
Secure evolvable hardware for public-key cryptosystems
New Generation Computing - Evolutionary computation
Integration, the VLSI Journal - Special issue: Embedded cryptographic hardware
Evolutionary Public-Key Cryptographic Circuits
IEA/AIE '08 Proceedings of the 21st international conference on Industrial, Engineering and Other Applications of Applied Intelligent Systems: New Frontiers in Applied Artificial Intelligence
VECPAR'02 Proceedings of the 5th international conference on High performance computing for computational science
Efficient hardware for modular exponentiation using the sliding-window method
International Journal of High Performance Systems Architecture
High speed systolic Montgomery modular multipliers for RSA cryptosystems
IMCAS'06 Proceedings of the 5th WSEAS international conference on Instrumentation, measurement, circuits and systems
A massively parallel hardware for modular exponentiations using the m-ary method
ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part II
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Modular multiplication is the most dominant part of the computation performed in public-key cryptography systems such as the RSA cryptosystem. The operation is time consuming for large operands. This paper describes the characteristics of two architectures designed toimplement modular multiplication using the fast Montgomery algorithm: the first FPGA prototype has an iterative sequential architecture while the second has a systolic array-based architecture. The paper compares both prototypes using the time 脳area classic factor.