Hardware Implementation of Montgomery's Modular Multiplication Algorithm
IEEE Transactions on Computers
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
High-Radix Montgomery Modular Exponentiation on Reconfigurable Hardware
IEEE Transactions on Computers
Montgomery's Multiplication Technique: How to Make It Smaller and Faster
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
Modular Exponent Realization on FPGAs
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
Montgomery Modular Exponentiation on Reconfigurable Hardware
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
Two Hardware Implementations for the Montgomery Modular Multiplication: Sequential versus Parallel
Proceedings of the 15th symposium on Integrated circuits and systems design
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The Secure Remote Password (SRP) protocol is an authentication and key-exchange protocol suitable for secure password verification and session key generation over insecure communication channels. The modular exponentiations involved, however, are very time-consuming, causing slow log-on procedures. This work presents the design of a hardware accelerator that performs modular exponentiation of very wide integers. The experimental platform is tutwlan, a Wireless Local Area Network (wlan) being developed at Tampere University of Technology. It runs on the Altera Excalibur development board that contains a microprocessor and a chip with programmable hardware. The results show that a full modular exponentiation with 1023-bit inputs can be performed in less than 40 ms using less than 10,000 logic elements, each consisting of a 4-input lookup table and a register. By using the implemented hardware accelerator in the authentication protocol, the execution time is reduced by a factor of 4. In addition, proposals to improve the implemented modular exponentiation architecture are presented. An additional factor of 5 improvement (totaling a factor of 20) can be achieved by implementing the fastest design.