A massively parallel hardware for modular exponentiations using the m-ary method

Authors:
Marcos Santana Farias;Sérgio de Souza Raposo;Nadia Nedjah;Luiza de Macedo Mourelle
Affiliations:
Department of Electronics Engineering and Telecommunications, State University of Rio de Janeiro, Brazil;Department of Electronics Engineering and Telecommunications, State University of Rio de Janeiro, Brazil;Department of Electronics Engineering and Telecommunications, State University of Rio de Janeiro, Brazil;Department of System Engineering and Computation, Engineering Faculty, State University of Rio de Janeiro, Brazil
Venue:
ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part II
Year:
2010

Citing 8
Cited 0

A method for obtaining digital signatures and public-key cryptosystems

Communications of the ACM
VHDL: Analysis and Modeling of Digital Systems

VHDL: Analysis and Modeling of Digital Systems
Efficient Parallel Modular Exponentiation Algorithm

ADVIS '02 Proceedings of the Second International Conference on Advances in Information Systems
Two Hardware Implementations for the Montgomery Modular Multiplication: Sequential versus Parallel

Proceedings of the 15th symposium on Integrated circuits and systems design
Fast Reconfigurable Hardware for the M-ary Modular Exponentiation

DSD '04 Proceedings of the Digital System Design, EUROMICRO Systems
Fast Parallel Exponentiation Algorithm for RSA Public-Key Cryptosystem

Informatica
Efficient Hardware for Modular Exponentiation using the Sliding-Window Method with Variable-Length Partitioning

ICYCS '08 Proceedings of the 2008 The 9th International Conference for Young Computer Scientists
High-performance hardware of the sliding-window method for parallel computation of modular exponentiations

International Journal of Parallel Programming - Special issue on the 19th international symposium on computer architecture and high performance computing (SBAC-PAD 2007)

Quantified Score

Hi-index	0.00

Visualization

Abstract

Most of cryptographic systems are based on modular exponentiation. It is performed using successive modular multiplications. One way of improving the throughput of a cryptographic system implementation is reducing the number of the required modular multiplications. Existing methods attempt to reduce this number by partitioning the exponent in constant or variable size windows. In this paper, in the purpose of further accelerating the computation of modular exponentiation, a concurrent novel approach is proposed along with hardware implementation of the concurrent m-ary method. We compare the proposed method to the sequential implementation.