A massively parallel hardware for modular exponentiations using the m-ary method
ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part II
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Modular exponentiation is an essential arithmetic operation for various applications, such as cryptography. The performance of this operations has a tremendous impact on the efficiency of the whole application. Therefore, many researchers devoted special interest to providing smart methods and efficient implementation for that operation. One of these methods is the sliding-window method, which pre-processes the exponent into zero and non-zero partitions. Zero partitions allow for a reduction of the number of modular multiplications required in the exponentiation process. In this paper, we devise two novel harwdare designs for computing modular exponentiation using the sliding-window method: one uses the constant-length non-zero partitions strategy (CLNZ) and the other uses the variable-length non-zero partitions strategy (VLNZ). The implementations are compared to existing hardware implementations of the modular exponentiation using the performace factor areaxtime.