Efficient and secure cryptographic systems based on addition chains: hardware design vs. software/hardware co-design

Authors:
Nadia Nedjah;Luiza de Macedo Mourelle
Affiliations:
Department of Electronics Engineering and Telecommunications, Faculty of Engineering, State University of Rio de Janeiro, Brazil;Department of Systems Engineering and Computation, Faculty of Engineering, State University of Rio de Janeiro, Brazil
Venue:
Integration, the VLSI Journal - Special issue: Embedded cryptographic hardware
Year:
2007

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Abstract

Most of cryptographic systems are based on modular exponentiation, wherein the operands are considerably large. Generally, modular exponentiation is implemented using a chain of modular multiplications. One way of improving the throughput of a cryptographic system implementation is reducing the number of the required modular multiplications. Given the exponent, finding the minimal number of multiplications that are necessary to reach the exponentiation results is a hard problem. We take advantage of an evolutionary stochastic process, commonly called genetic algorithms, to compute minimal addition chains, allow us to reduce drastically the number of the required modular multiplications. In this paper, we investigate two different ways to implement modular exponentiation based on the evolved addition chain: the first approach consists of implementing all the exponentiation operation on hardware and the second approach combines software and hardware. While the first approach attempts to optimise the encryption/decryption throughput regardless of the cost of system implementation, the second attempts to reach a balance between the throughput and the cost of the implementation.