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On the reconfiguration of degradable VLSI/WSI arrays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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IEEE Transactions on Computers
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IEEE Transactions on Computers
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Proceedings of the twentieth annual symposium on Parallelism in algorithms and architectures
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Transactions on computational science XIII
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This paper considers the problem of reconfiguring two-dimensional degradable VLSI/WSI arrays under the constraint of row and column rerouting. The goal of the reconfiguration problem is to derive a fault-free subarray $T$ from the defective host array such that the dimensions of $T$ are larger than some specified minimum. This problem has been shown to be NP-complete under various switching and routing constraints. However, we show that a special case of the reconfiguration problem is optimally solvable in linear time. Using this result, a new fast and efficient reconfiguration algorithm is proposed. Empirical study shows that the new algorithm indeed produces good results in terms of the percentages of harvest and degradation of VLSI/WSI arrays.