New Architecture and Algorithms for Degradable VLSI/WSI Arrays

Authors:
Wu Jigang;Heiko Schröder;Srikanthan Thambipillai
Affiliations:
-;-;-
Venue:
COCOON '02 Proceedings of the 8th Annual International Conference on Computing and Combinatorics
Year:
2002

Citing 9
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Abstract

The problem of reconfiguring a two-dimensional degradable VLSI/WSI array under the row and column routing constraints is NP-complete. This paper aims to decrease gate delay and increase the harvest. A new architecture with six-port switches is proposed. New greedy rerouting algorithms and new compensation approaches are presented and used to reform the reconfiguration algorithm. Experimental results show that the new reconfiguration algorithm consistently outperforms the latest algorithm, both in terms of the percentages of harvest and that of degradation of VLSI/WSI array.