A Run-time Reconfiguration Algorithm for VLSI Arrays

Authors:
Wu Jigang;Srikanthan Thambipillai
Affiliations:
-;-
Venue:
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Year:
2003

Citing 10
Cited 0

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Abstract

This paper discusses the NP-complete problem of reconfiguringa two-dimensional degradable VLSI/WSI array underthe row and column routing constraints. A new strategyfor row selection in the logical array is proposed andthe earlier approach by Low et. al. is simplified. A flawin Low's algorithm is also addressed. Experimental resultsshow that our algorithm is approximately 50% faster thanthe most efficient algorithm, cited in the literature, withoutloss of performance.