On the reconfiguration algorithm for fault-tolerant VLSI arrays

Authors:
Jigang Wu;Srikanthan Thambipillai
Affiliations:
Centre for High Performance Embedded Systems, Nanyang Technological University, Singapore;Centre for High Performance Embedded Systems, Nanyang Technological University, Singapore
Venue:
ICCS'03 Proceedings of the 2003 international conference on Computational science: PartIII
Year:
2003

Citing 11
Cited 1

Configuration of VLSI Arrays in the Presence of Defects

Journal of the ACM (JACM)
A Study of Two Approaches for Reconfiguring Fault-Tolerant Systolic Arrays

IEEE Transactions on Computers
Fault Tolerance in VLSI Circuits

Computer
A Comprehensive Reconfiguration Scheme for Fault-Tolerant VLSI/WSI Array Processors

IEEE Transactions on Computers
Fault-Tolerant Processor Arrays Based on the 1$\frac{1}{2}$-Track Switches with Flexible Spare Distributions

IEEE Transactions on Computers
An Efficient Reconfiguration Algorithm for Degradable VLSI/WSI Arrays

IEEE Transactions on Computers
Harvesting Through Array Partitioning: A Solution to Achieve Defect Tolerance

DFT '97 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems
Efficient Spare Allocation for Reconfigurable Arrays

IEEE Design & Test
Wafer-Scale Integration of Systolic Arrays

IEEE Transactions on Computers
Fault-Tolerant Design for VLSI: Effect of Interconnect Requirements on Yield Improvement of VLSI Designs

IEEE Transactions on Computers
On the reconfiguration of degradable VLSI/WSI arrays

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Preprocessing and partial rerouting techniques for accelerating reconfiguration of degradable VLSI arrays

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Abstract

In this paper, an improved algorithm is presented for the NP-complete problem of reconfiguring a two-dimensional degradable VLSI array under the row and column routing constraints. The proposed algorithm adopts the partial computing for the logical row exclusion so that the most efficient algorithm, cited in literature, is speeded up without loss of performance. In addition, a flaw in the earlier approach is also addressed. Experimental results show that our algorithm is approximately 50% faster than the above stated algorithm.