Preprocessing and partial rerouting techniques for accelerating reconfiguration of degradable VLSI arrays

Authors:
Wu Jigang;Thambipillai Srikanthan;Xiaogang Han
Affiliations:
School of Computer Technology and Automation, Tianjin Polytechnic University, Tianjin, China;School of Computer Engineering, Nanyang Technological University, Singapore, Singapore;School of Computer Engineering, Nanyang Technological University, Singapore, Singapore
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2010

Citing 7
Cited 0

An Efficient Reconfiguration Algorithm for Degradable VLSI/WSI Arrays

IEEE Transactions on Computers
An improved reconfiguration algorithm for degradable VLSI/WSI arrays

Journal of Systems Architecture: the EUROMICRO Journal
A Genetic Approach for the Reconfiguration of Degradable Processor Arrays

DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Reconfiguration Algorithms for Power Efficient VLSI Subarrays with Four-Port Switches

IEEE Transactions on Computers
Integrated Row and Column Rerouting for Reconfiguration of VLSI Arrays with Four-Port Switches

IEEE Transactions on Computers
On the reconfiguration algorithm for fault-tolerant VLSI arrays

ICCS'03 Proceedings of the 2003 international conference on Computational science: PartIII
On the reconfiguration of degradable VLSI/WSI arrays

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents novel techniques to accelerate the reconfiguration of degradable very large scale integration arrays. A preprocessing step is used to derive the upper and lower size bounds of the maximum logical array (MLA) such that only those subarrays that possibly contain the MLA are reconfigured, thereby reducing the reconfiguration time and also obtaining a same-sized logical array. In addition, the partial rerouting approach is generalized so that as many as possible previous routing results can be reused in the current rerouting step. The reconfiguration time is reduced from O((1 - ρ) ċ β m ċ n) to its lower bound O((1 - ρ) ċ m ċ n) for m × n host arrays with small fault density ρ, where β is the expected routing length required per logical column.