A Genetic Approach for the Reconfiguration of Degradable Processor Arrays

Authors:
Masaru Fukushi;Yusuke Fukushima;Susumu Horiguchi
Affiliations:
Tohoku University;Tohoku University;Tohoku University
Venue:
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Year:
2005

Citing 0
Cited 4

Integrated Row and Column Rerouting for Reconfiguration of VLSI Arrays with Four-Port Switches

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Defect tolerance in homogeneous manycore processors using core-level redundancy with unified topology

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On topology reconfiguration for defect-tolerant NoC-based homogeneous manycore systems

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Preprocessing and partial rerouting techniques for accelerating reconfiguration of degradable VLSI arrays

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Abstract

This paper discusses the NP-complete problem of reconfiguring two-dimensional degradable processor arrays under the row and column rerouting constraints. One major drawback of the previous algorithms is that a rerouting scheme to construct logical rows/columns can be applied only in one direction, either row or column direction, to handle the difficulty of this reconfiguration problem. We propose a new approach for the reconfiguration of degradable processor arrays employing a genetic algorithm (GA). The GA is used to evolve rerouting strategies for constructing logical rows/columns. A strategy based rerouting scheme is proposed to reroute the inter-connections of fault-free PEs in both row and column directions. The performances of our algorithm are compared with previous studies and it indicates that the proposed algorithm achieves better results in terms of harvest and degradation.