A Polynomial Time Algorithm for Reconfiguring Multiple-Track Models

Authors:
T. A. Varvarigou;V. P. Roychowdhury;T. Kailth
Affiliations:
-;-;-
Venue:
IEEE Transactions on Computers
Year:
1993

Citing 5
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The Full-Use-of-Suitable-Spares (FUSS) Approach to Hardware Reconfiguration for Fault-Tolerant Processor Arrays

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New algorithms for reconfiguring VLSI/WSI arrays

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Reconfiguring Processor Arrays Using Multiple-Track Models: The 3Track-Spare-Approach

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Reconfiguration for fault tolerance using graph grammars

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Fault-Tolerant Processor Arrays Based on the 1$\frac{1}{2}$-Track Switches with Flexible Spare Distributions

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Reconfiguring Processor Arrays Using Multiple-Track Models: The 3Track-Spare-Approach

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An Analysis for Fault-Tolerant 3D Processor Arrays Using 1.5-Track Switches

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Abstract

A polynomial time algorithm for solving the combinatorial problem that underlies the reconfiguration issues in the m1/2-track-m-spare model, for any arbitrary m, is discussed. The following combinatorial problem is solved: Given a set of points in a two-dimensional grid, find a set of noninteracting straight lines such that every line starts at a point and connects to one of the boundaries of the grid, there are no more than m lines overlapping in any row or column of the grid, and there are no near-miss situations. The time complexity of the algorithm is shown to be O(m mod F mod /sup 2/), where mod F is the number of faulty processors.