Configuration of VLSI Arrays in the Presence of Defects
Journal of the ACM (JACM)
VLSI array processors
Combinatorial optimization: algorithms and complexity
Combinatorial optimization: algorithms and complexity
Fault-Tolerant Array Processors Using Single-Track Switches
IEEE Transactions on Computers
A fast algorithm for connecting grid points to the boundary with nonintersecting straight lines
SODA '91 Proceedings of the second annual ACM-SIAM symposium on Discrete algorithms
Fault-tolerant meshes with small degree
SPAA '93 Proceedings of the fifth annual ACM symposium on Parallel algorithms and architectures
Efficient breakout routing in printed circuit boards
SCG '97 Proceedings of the thirteenth annual symposium on Computational geometry
Node-covering, Error-correcting Codes and Multiprocessors with Very High Average Fault Tolerance
IEEE Transactions on Computers
Efficient algorithms for finding disjoint paths in grids
SODA '97 Proceedings of the eighth annual ACM-SIAM symposium on Discrete algorithms
Escaping a grid by edge-disjoint paths
SODA '00 Proceedings of the eleventh annual ACM-SIAM symposium on Discrete algorithms
IEEE Transactions on Computers
A Polynomial Time Algorithm for Reconfiguring Multiple-Track Models
IEEE Transactions on Computers
Reconfigurability and Reliability of Systolic/Wavefront Arrays
IEEE Transactions on Computers
Fault-Tolerant Meshes and Hypercubes with Minimal Numbers of Spares
IEEE Transactions on Computers
Reconfiguring Processor Arrays Using Multiple-Track Models: The 3Track-Spare-Approach
IEEE Transactions on Computers
A Faster Algorithm for Finding Disjoint Paths in Grids
ISAAC '99 Proceedings of the 10th International Symposium on Algorithms and Computation
Reconfigurable architectures for mesh-arrays with PE and link faults
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Ordered escape routing based on Boolean satisfiability
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
On using SAT to ordered escape problems
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A dynamically reconfigurable interconnect for array processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The issue of developing efficient algorithms for reconfiguring processor arrays in the presence of faulty processors and fixed hardware resources is discussed. The models discussed consist of a set of identical processors embedded in a flexible interconnection structure that is configured in the form of a rectangular grid. An array grid model based on single-track switches is considered. An efficient polynomial time algorithm is proposed for determining feasible reconfigurations for an array with a given distribution of faulty processors. In the process, it is shown that the set of conditions in the reconfigurability theorem is not necessary. A polynomial time algorithm is developed for finding feasible reconfigurations in an augmented single-track model and in array grid models with multiple-track switches.