Reconfigurable architectures for mesh-arrays with PE and link faults

Authors:
I. Takanami;T. Horita
Affiliations:
-;-
Venue:
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Year:
1995

Citing 5
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Abstract

We propose reconstruction architectures for mesh-arrays with link faults as well as processor element (PE) faults. First, we explain a method for compensating link faults and give a compensation algorithm for the case where no PE is faulty. Then, the reliabilities of the proposed interconnection networks are obtained by computer simulation and are compared with that of the network with doubly duplicated links. Next, we show how PE faults are compensated using the proposed network. It is seen that when no link is faulty, the ability of compensation is greater than that of the reconstruction strategy using single-track switches but is less than that of the strategy allowing the horizontal or vertical compensation paths to the spares on the boundary of mesh-arrays to cross. Finally considering that the proposed architectures have several routes to connect healthy PEs with each other, avoiding faulty PE, we propose an algorithm for coping with simultaneous faults of PEs and interconnection links.