Configuration of VLSI Arrays in the Presence of Defects
Journal of the ACM (JACM)
Testing for cycles in infinite graphs with periodic structure
STOC '87 Proceedings of the nineteenth annual ACM symposium on Theory of computing
VLSI array processors
Fault-Tolerant Array Processors Using Single-Track Switches
IEEE Transactions on Computers
A scalable architecture for lattice-gas simulations
Journal of Computational Physics
Efficient Algorithms for Reconfiguration in VLSI/WSI Arrays
IEEE Transactions on Computers
A semiring on convex polygons and zero-sum cycle problems
SIAM Journal on Computing
| Hi-index | 14.98 |
The authors study fault-tolerant redundant structures for maintaining reliable arrays. In particular, they assume that the desired array (application graph) is embedded in a certain class of regular, bounded-degree graphs called dynamic graphs. The degree of reconfigurability (DR) and DR with distance (DR/sup d/) of a redundant graph are defined. When DR and DR/sup d/ are independent of the size of the application graph, the graph is finitely reconfigurable (FR) and locally reconfigurable (LR), respectively. It is shown that DR provides a natural lower bound on the time complexity of any distributed reconfiguration algorithm and that there is no difference between being FR and LR on dynamic graphs. It is also shown that if both local reconfigurability and a fixed level of reliability are to be maintained, a dynamic graph must be of a dimension at least one greater than the application graph. Thus, for example, a one-dimensional systolic array cannot be embedded in a one-dimensional dynamic graph without sacrificing either reliability or locality of reconfiguration.