Efficient Algorithms for Reconfiguration in VLSI/WSI Arrays
IEEE Transactions on Computers
Efficient algorithms for finding disjoint paths in grids
SODA '97 Proceedings of the eighth annual ACM-SIAM symposium on Discrete algorithms
Monotonic parallel and orthogonal routing for single-layer ball grid array packages
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A routing algorithm for flip-chip design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
An integer linear programming based routing algorithm for flip-chip design
Proceedings of the 44th annual Design Automation Conference
Ordered escape routing based on Boolean satisfiability
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Ordered escape routing via routability-driven pin assignment
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Recent research development in PCB layout
Proceedings of the International Conference on Computer-Aided Design
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Routing for high-speed boards is largely a time-consuming manual task today. The ordered escape routing problem is one of the key problems in board-level routing, and Boolean Satisfiability (SAT) based approach [1] is the only solution to this problem so far. In this paper, we first solve the major deficiency of the original SAT formulation so that the escape problem is completely resolved. Then we propose two techniques to extend SAT approach for large-scale problems. Experimental results on industrial benchmarks show that our methods perform well in terms of both speed and routability.