Efficient algorithms for finding disjoint paths in grids
SODA '97 Proceedings of the eighth annual ACM-SIAM symposium on Discrete algorithms
General river routing algorithm
DAC '83 Proceedings of the 20th Design Automation Conference
Monotonic parallel and orthogonal routing for single-layer ball grid array packages
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A routing algorithm for flip-chip design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
An integer linear programming based routing algorithm for flip-chip design
Proceedings of the 44th annual Design Automation Conference
Ordered escape routing based on Boolean satisfiability
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
On using SAT to ordered escape problems
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
An improved optimal algorithm for bubble-sorting-based non-Manhattan channel routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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For board-level routing, ordered escape routing is a key problem. In this paper, based on the optimality of hierarchical bubble sorting, the process of assigning routability-driven pins is done for single-layer routing. Furthermore, an efficient routing approach with the consideration of variable capacity is proposed to solve the ordered escape routing problem. The experimental results show that our proposed approach achieves 100% routability for the tested examples in reasonable CPU time. Compared with the SAT-based approach[6] for the tested examples with the capacity 1, our proposed approach reduces the CPU time by 77.7% on the average. For the tested examples with the capacity 2, our proposed approach can achieve 100% routability in reasonable CPU time.