Reconfiguring Fault-Tolerant Two-Dimensional Array Architectures

Authors:
Nathaniel J. Davis, IV;F. Gail Gray;Joseph A. Wegner;Shannon E. Lawson;Vinay Murthy;Tennis S. White
Affiliations:
-;-;-;-;-;-
Venue:
IEEE Micro
Year:
1994

Citing 4
Cited 0

On Fault-Tolerant Structure, Distributed Fault-Diagnosis, Reconfiguration, and Recovery of the Array Processors

IEEE Transactions on Computers
Efficient Algorithms for Reconfiguration in VLSI/WSI Arrays

IEEE Transactions on Computers
Distributed control reconfiguration algorithms for two-dimensional mesh architectures

Distributed control reconfiguration algorithms for two-dimensional mesh architectures
A fault-tolerant cellular architecture (arrays, testing)

A fault-tolerant cellular architecture (arrays, testing)

Quantified Score

Hi-index	0.00

Visualization

Abstract

Circuit complexities reduce overall reliability and mean-time-between-failure rates of today's very large processing arrays. Our integrated, three-level hierarchy of reconfiguration methods provides reasonable levels of fault tolerance for such systems. Operating in a completely distributed fashion, the hierarchy does not require that any components be fault free. It significantly improves array reliability by using a combination of transient fault rollback techniques and local and global reconfiguration algorithms.