Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
Performance Analysis of k-ary n-cube Interconnection Networks
IEEE Transactions on Computers
Performance of multicomputer networks under Pin-out constraints
Journal of Parallel and Distributed Computing
The turn model for adaptive routing
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
A New Theory of Deadlock-Free Adaptive Routing in Wormhole Networks
IEEE Transactions on Parallel and Distributed Systems
Compressionless routing: a framework for adaptive and fault-tolerant routing
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
An efficient, fully adaptive deadlock recovery scheme: DISHA
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
A 100 Mbps, LED through-wafer optoelectronic link for multicomputer interconnection networks
Journal of Parallel and Distributed Computing - Special issue on parallel computing with optical interconnects
Embeddings of star graphs into optical meshes without bends
Journal of Parallel and Distributed Computing
High-Throughput, Low-Memory Applications on the Pica Architecture
IEEE Transactions on Parallel and Distributed Systems
Hierarchical Scalable Photonic Architectures for High-Performance Processor Interconnection
IEEE Transactions on Computers
Limits on Interconnection Network Performance
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Parallel and Distributed Systems
The Impact of Pipelined Channels on k-ary n-Cube Networks
IEEE Transactions on Parallel and Distributed Systems
A Necessary and Sufficient Condition for Deadlock-Free Adaptive Routing in Wormhole Networks
IEEE Transactions on Parallel and Distributed Systems
An Optical Interconnect Model for k-ary n-cube Wormhole Networks
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
Three-Dimensional Network Topologies
PCRCW '94 Proceedings of the First International Workshop on Parallel Computer Routing and Communication
The Offset Cube: An Optoelectronic Interconnection Network
PCRCW '94 Proceedings of the First International Workshop on Parallel Computer Routing and Communication
Design of a terabit free-space photonic backplane for parallel computing
MPPOI '95 Proceedings of the Second Workshop on Massively Parallel Processing Using Optical Interconnections
Design of a Compact Alignment Tolerant Optical Interconnect for Photonic Backplane Applications
MPPOI '97 Proceedings of the 4th International Conference on Massively Parallel Processing Using Optical Interconnections
Applying Optical Interconnects to Electronic Systems Promis vs. Practicality
MPPOI '97 Proceedings of the 4th International Conference on Massively Parallel Processing Using Optical Interconnections
High-Throughput, Low-Memory Applications on the Pica Architecture
IEEE Transactions on Parallel and Distributed Systems
An Analysis for Fault-Tolerant 3D Processor Arrays Using 1.5-Track Switches
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Design of a viable fault-tolerant routing strategy for optical-based grids
ISPA'03 Proceedings of the 2003 international conference on Parallel and distributed processing and applications
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Three-dimensional packaging technologies are critical for enabling ultra-compact, massively parallel processors (MPPs) for embedded applications. Through-wafer optical interconnect has been proposed as a useful technology for building ultra-compact MPPs since it provides a simplified mechanism for interconnecting stacked multichip substrates. This paper presents the offset cube, a new network topology designed to exploit the packaging benefits of through-wafer optical interconnect in ultra-compact MPP systems. We validate the offset cube's topological efficiency by developing deadlock-free adaptive routing protocols with modest virtual channel requirements (only two virtual channels per link needed for full adaptivity). A preliminary analysis of router complexity suggests these protocols can be efficiently implemented in hardware. We also present a 3D mesh embedding for the offset cube. Network simulations show the offset cube performs comparably to a bidirectional 3D mesh of equal size under uniform, hot-spot, and trace-driven traffic loads. While the offset cube is not proposed as a general replacement for the mesh topology, it leverages the benefits of through-wafer optical interconnect more effectively than a mesh by completely eliminating chip-to-chip wires for data signals. Hence, the offset cube is an effective topology for interconnecting ultra-compact MCM-level MPP systems.