Introduction to VLSI Systems
Distributed fault-tolerance for large multiprocessor systems
ISCA '80 Proceedings of the 7th annual symposium on Computer Architecture
A large scale, homogeneous, fully distributed parallel machine, I
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
Configuration of VLSI Arrays in the Presence of Defects
Journal of the ACM (JACM)
Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems
IEEE Transactions on Computers
Efficient embeddings of binary trees in VLSI arrays
IEEE Transactions on Computers
On group graphs and their fault tolerance
IEEE Transactions on Computers
Optimal Graph Algorithms on a Fixed-Size Linear Array
IEEE Transactions on Computers
On an Optimally Fault-Tolerant Multiprocessor Network Architecture
IEEE Transactions on Computers
IEEE Transactions on Computers
The Cubical Ring Connected Cycles: A Fault Tolerant Parallel Computation Network
IEEE Transactions on Computers
IEEE Transactions on Computers
A Multiple Fault-Tolerant Processor Network Architecture for Pipeline Computing
IEEE Transactions on Computers
A novel approach to system-level fault tolerance in hypercube multiprocessors
C3P Proceedings of the third conference on Hypercube concurrent computers and applications: Architecture, software, computer systems, and general issues - Volume 1
Fault-Tolerant Array Processors Using Single-Track Switches
IEEE Transactions on Computers
On the Design of Fault-Tolerant Two-Dimensional Systolic Arrays for Yield Enhancement
IEEE Transactions on Computers
On Implementing Large Binary Tree Architectures in VLSI and WSI
IEEE Transactions on Computers
Optimal Matrix Multiplication on Fault-Tolerant VLSI Arrays
IEEE Transactions on Computers
Restructuring for Fault-Tolerant Systolic Arrays
IEEE Transactions on Computers
Reconfiguration of VLSI/WSI Mesh Array Processors with Two-Level Redundancy
IEEE Transactions on Computers
A Study of Two Approaches for Reconfiguring Fault-Tolerant Systolic Arrays
IEEE Transactions on Computers
IEEE Transactions on Computers
Reconfigurable Multipipelines for Vector Supercomputers
IEEE Transactions on Computers
Fault Tolerance in VLSI Circuits
Computer
Algorithm-Based Fault Tolerance on a Hypercube Multiprocessor
IEEE Transactions on Computers
Self-Diagnosis of Failures in VLSI Tree Array Processors
IEEE Transactions on Computers
Bi-Level Reconfigurations of Fault Tolerant Arrays
IEEE Transactions on Computers
Embedding tree structures in massively parallel computers
SAC '95 Proceedings of the 1995 ACM symposium on Applied computing
Diagnosis by Signature Analysis of Test Responses
IEEE Transactions on Computers
Computational Arrays with Flexible Redundancy
IEEE Transactions on Computers
Fault-tolerant wafer-scale architectures for VLSI
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
Fault-secure algorithms for multiple-processor systems
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
A General Reconfiguration Technique for Fault Tolerant Processor Architectures
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
The Diogenes Approach to Testable Fault-Tolerant Arrays of Processors
IEEE Transactions on Computers
On Area and Yield Considerations for Fault-Tolerant VLSI Processor Arrays
IEEE Transactions on Computers
Embedding Tree Structures in VLSI Hexagonal Arrays
IEEE Transactions on Computers
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Multiprocessor arrays have the property of regularity, enabling a low-cost VLSI implementation. However, multiprocessor systems with a fixed structure tend to be error prone and restricted to specialized applications, which makes them less attractive to the semiconductor industry. Consequently, reconfigurability and fault-tolerance are desirable features of a multiprocessor array. A multiprocessor array with a flexible structure can be adapted to many applications and may restructure itself upon failure of a processor, to avoid using faulty processors. The objective of this work is to demonstrate the feasibility of a multiprocessor array having these properties. An example of such an array is introduced, and distributed structuring algorithms for it are presented. A novel strategy for internal testing and for identification of faulty processors is developed, and the structuring algorithms are modified to accommodate faulty processors.